The present invention relates to a semiconductor device.
One of protection measures against runaway of a CPU (Central Processing Unit) that is incorporated into electronic equipment or the like is use of a watchdog timer. The watchdog timer does not operate forever when the CPU to be monitored is in normal condition. However, the watchdog timer needs to operate properly when the CPU comes in abnormal condition. Therefore, enhancement of the reliability of the watchdog timer is important to respond to CPU anomaly.
Japanese Unexamined Patent Application Publication No. 2003-131906 discloses a technique to check the operation of a watchdog timer. Electronic equipment disclosed therein has two watchdog timers for a CPU. Each watchdog timer has an internal counter and performs counting. The CPU supplies watchdog clear signals to the two watchdog timers. When the watchdog clear signal is supplied, each watchdog timer clears the internal count value. When the count value overflows, the watchdog timer supplies a reset signal to a logical connector. When reset signals from the two watchdog timers are supplied to the logical connector, the logical connector supplies a reset signal to the CPU. Thus, the CPU is not reset when the reset signal is output from only one watchdog timer.
The CPU intentionally stops one watchdog clear signal during operation and determines whether the watchdog timer to which the signal has been supplied operates properly. In other words, the CPU determines whether the watchdog timer outputs a reset signal or not. By the above operation, the electronic equipment disclosed in Japanese Unexamined Patent Application Publication No. 2003-131906 can determine whether the watchdog timer operates properly during the operation of the CPU.